1. Technical Field
This disclosure relates to a single crystalline structure, a method of forming the same, a semiconductor device having the single crystalline structure, and method of manufacturing the semiconductor device. More particularly, the disclosure relates to a single crystalline structure having a shape that is suitable for vertically stacking semiconductor unit elements, a method of forming the single crystalline structure, a semiconductor device having the single crystalline structure, and a method of manufacturing the semiconductor device.
2. Description of the Related Art
To continuously improve an integration degree of a semiconductor device, a line width of a pattern formed on a semiconductor chip and/or an interval between two adjacent patterns has been gradually narrowed. Generally, when the line width or the interval of the patterns is gradually narrowed, an electrical resistance of the patterns is greatly increased. Thus, there is a limit in increasing the integration degree by reducing the size of the pattern. To highly integrate the semiconductor device, a vertically stacked semiconductor device having a plurality of the semiconductor unit elements that are vertically stacked on a semiconductor substrate has been recently developed.
To manufacture the vertically stacked semiconductor device, an active region is formed in a predetermined region of the semiconductor substrate. A single crystalline structure used for the active region is formed on the semiconductor substrate. An example of the single crystalline structure includes a single crystalline silicon material.
To form the single crystalline structure on the active region, a selective epitaxial growth (SEG) process for forming a single crystalline silicon layer on the semiconductor substrate as a seed and a chemical mechanical polishing (CMP) process for planarizing the single crystalline silicon layer are performed.
A conventional method of manufacturing a single crystalline silicon structure by an SEG process is disclosed in U.S. Pat. No. 5,554,870,to Fitch, et al. (“Fitch”). In the conventional method disclosed by Fitch, after forming an insulation pattern having an opening that exposes a seed, a source gas is provided onto the seed so that an epitaxial layer including a single crystalline silicon material grows on the seed.
However, when the conventional epitaxial layer grows on the seeds, a portion of the epitaxial layer frequently makes contact with an inside wall of the opening of the insulation pattern. When the portion of the epitaxial layer makes contact with the inside wall of the opening, the source gas is not provided to a region under a contact region where the inside wall and the epitaxial layer make contact.
FIG. 1 is a cross sectional diagram illustrating a single crystalline silicon structure formed by the conventional epitaxial growth method. Referring to FIG. 1, an insulating pattern 12 is formed on a semiconductor substrate 10. When an epitaxial layer 14 is grown on the structure as a single crystalline silicon structure, a void 20 is generated in the lower region because a source gas is not provided into the lower region. The reliability of semiconductor devices having the void 20 may be greatly reduced.
Embodiments of the invention address these and other disadvantages of the conventional art.